1. Field of the Invention
Exemplary embodiments of the present invention relates to a method for fabricating a semiconductor device, and, more particularly, to a high-voltage semiconductor device.
2. Description of Related Art
In general, integrated, circuits each including more than one high-voltage transistors arrayed on a chip along with low-voltage circuits are widely used in diverse electrical application fields. Among the high-voltage semiconductor devices which hold significant positions in the integrated circuits are an extended drain MOS (EDMOS) transistor and a laterally double diffused MOS (LDMOS) transistor.
It is well known that resistivity or specific on resistance RSP should be decreased in order to improve an operation characteristic of a high-voltage semiconductor devise.
FIG. 1 is a cross-sectional view illustrating conventional EDMOS transistor. In the drawing, an EDMOS transistor having an N channel is exemplarily illustrated.
Referring to FIG. 1, the conventional EDMOS transistor includes a P-type first well 12 and an N-type second well 13 formed over a substrate 11 with a device isolation layer 18 formed therein to contact each other, a gate electrode 12 simultaneously crossing the P-type first well 12 and the N-type second well 13 over the substrate 11, a gate insulation layer 16 interposed between the gate electrode 17 and the substrate 11, an N-type source region 14 formed over the P-type first well 12 on one side of the gate electrode 17, an N-type drain region 19 formed over the N-type second well 13 on another side of the gate electrode 17, and a P-type pickup region 15 formed over the P-type first well 12.
In an EDMOS transistor having the above structure, a specific on resistance RSP is defined as a multiplication of an on resistance RON by a half-pitch HP, which is the length of the transistor, by the width W of the transistor (RSP=RON×HP×w). Herein, the half-pitch HP is defined as a distance from the N-type source region 14 to the N-type drain region 19, and the on resistance RON is defined as a summation of a channel resistance RCH of a channel region C, an accumulation resistance RACC of an accumulation region A, a drift resistance RDRIFT of a drift region D, and other resistances REST of the other regions (RON=RCH+RACC+RDRIFT+REXT).
However, a conventional semiconductor device characteristic has its channel resistance RCH increasing in direct proportion to an of channel length. For this reason, when the effective channel length increases, the channel resistance RCH increases as well to thereby increase the specific on resistance RSP.
In particular, the P-type first well 12 and the N-type second well 13 for a high-voltage semiconductor device are formed by sequentially performing an ion implantation process and a thermal treatment for activating implanted impurities. However, since the P-type first well 12 and the N-type second well 13 have different conductive types, an increase in the effective channel length originating from the lateral diffusion of the impurities implanted during the thermal treatment function as a direct cause for deteriorated on resistance RON. To be specific, due to the difference in the lateral diffusion speeds of the impurities implanted into the P-type first well 12 and the N-type second well 13 during the thermal treatment for forming the 2-type first well 12 and the N-type second well 13, the position of the interface between the P-type first well 12 and the N-type second well 13 moves toward the ft type second well 13 from a predetermined position to thereby increase the effective channel length. As the effective channel length increases, the on resistance RON characteristic is deteriorated, which is problematic.
The deterioration in the on resistance RON caused by the lateral, diffusion is accelerated during a subsequent thermal treatment, and not only the EDMOS transistor but also an LDMOS transistor have the same problem or deteriorated on resistance RON caused by the lateral diffusion.